MAX5500AGAP データシートの表示（PDF） - Maxim Integrated

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MAX5500AGAP

Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Low-Power, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

Table 1. Serial-Interface Programming Commands

16-BIT SERIAL WORD

A1

A0

C1

C0

D11................D0

MSB

LSB

FUNCTION

0

0

0

1 12-bit DAC data Load input register A; DAC registers unchanged.

0

1

0

1 12-bit DAC data Load input register B; DAC registers unchanged.

1

0

0

1 12-bit DAC data Load input register C; DAC registers unchanged.

1

1

0

1 12-bit DAC data Load input register D; DAC registers unchanged.

0

0

1

1 12-bit DAC data Load input register A; all DAC registers updated.

0

1

1

1 12-bit DAC data Load input register B; all DAC registers updated.

1

0

1

1 12-bit DAC data Load input register C; all DAC registers updated.

1

1

1

1 12-bit DAC data Load input register D; all DAC registers updated.

0

1

0

0 XXXXXXXXXXXX Update all DAC registers from their respective input registers (startup).

1

0

0

0 12-bit DAC data Load all DAC registers from shift register (startup).

1

1

0

0 XXXXXXXXXXXX Shutdown (provided PDL = 1)

0

0

1

0 XXXXXXXXXXXX UPO goes low (default)

0

1

1

0 XXXXXXXXXXXX UPO goes high

0

0

0

0 XXXXXXXXXXXX No operation (NOP) to DAC registers

1

1

1

0 XXXXXXXXXXXX Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers updated.

1

0

1

0

XXXXXXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers updated

(default).

Figure 5 shows the serial-interface timing requirements.

The CS input must be low to enable the DAC’s serial

interface. When CS is high, the interface control circuitry

is disabled. CS must go low for at least tCSS before the

rising serial clock (SCLK) edge to properly clock in the

first bit. When CS is low, data is clocked into the internal

shift register through the serial data input (DIN) on the

rising edge of SCLK. The maximum guaranteed clock

frequency is 10MHz. Data is latched into the appropriate

input/DAC registers on the rising edge of CS.

The programming command “load-all-dacs-from-shift-

register” allows all input and DAC registers to be simul-

taneously loaded with the same digital code from the

input shift register. The no operation (NOP) command

leaves the register contents unaffected. This feature is

used in a daisy-chain configuration (see the Daisy

Chaining Devices section).

The command to change the clock edge on which seri-

al data is shifted out of DOUT also loads data from all

input registers to their respective DAC registers.

Serial-Data Output (DOUT)

The serial-data output, DOUT, is the internal shift regis-

ter’s output. The MAX5500/MAX5501 can be pro-

grammed so that data is clocked out of DOUT on the

rising edge of SCLK (mode 1) or the falling edge (mode

0). In mode 0, output data at DOUT lags input data at

DIN by 16.5 clock cycles, maintaining compatibility with

MICROWIRE, SPI/QSPI, and other serial interfaces. In

mode 1, output data lags input data by 16 clock cycles.

On power-up, DOUT defaults to mode 0 timing.

User-Programmable Logic Output (UPO)

The user-programmable logic output, UPO, allows an

external device to be controlled through the

MAX5500/MAX5501 serial interface (Table 1).

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