PEB 2465
1.3 Pin Definition and Functions
Pin No. Symbol Input (I) Function
Output (O)
General Description
Common Pins for All Channels
23
VDDD
I
58
GNDD I
40
VDDA12
I
9
VDDA34
I
27
FSC
I
26
DCL
I
25
DU
O
24
DD
I
22
RESET I
57
MODE I
60
TSS0 I
59
TSS1 I
56
TCK
I
55
TMS
I
54
TDI
I
53
TDO
O
28
LGKM0 O
21
LGKM1 O
41
VH12
I/O
8
VH34
I/O
+ 5 V supply for the digital circuitry 1)
Ground Digital, not internally connected to
GNDA 1, 2, 3, 4
All digital signals are referred to this pin
+ 5 V Analog supply voltage for channel 1 and 2 1)
+ 5 V Analog supply voltage for channel 3 and 4 1)
IOM-2: Frame synchronization clock , 8 kHz
IOM-2: Data clock, 2048 kHz or 4096 kHz depending
on MODE
IOM-2: Data upstream, open drain output
IOM-2: Data downstream, input
Reset input - forces the device to the default mode,
active high
IOM-2: Mode Selection
IOM-2: Time slot selection pin 0
IOM-2: Time slot selection pin 1
Boundary scan: Test Clock
Boundary scan: Test Mode Select
Boundary scan: Test Data Input
Boundary scan: Test Data Output
Loop/Ground Key Multiplexing output 0 for
channel 1, 2
Loop/Ground Key Multiplexing output 1 for
channel 3, 4
Reference voltage for channel 1 and 2, has to be
connected via a 220 nF cap. to ground
Reference voltage for channel 3 and 4, has to be
connected via a 220 nF cap. to ground
1) A 100 nF cap. should be used for blocking these pins, see also on page 87.
Semiconductor Group
11
02.97