RT8253A データシートの表示（PDF） - Richtek Technology
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RT8253A Datasheet PDF : 15 Pages
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RT8253A
Input Capacitor Selection
Voltage rating and current rating are the key parameters
in selecting the input capacitor. Generally, the input
capacitor should have a voltage rating 1.5 times greater
than the maximum input voltage to be considered a
conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
IIN_RMS = ILOAD x
VOUT
VIN
x
⎛
⎜1−
⎝
VOUT
VIN
⎞
⎟
⎠
The next step is to select a proper capacitor for RMS
current rating. For a good design use more than one
capacitor with low Equivalent Series Resistance (ESR) in
parallel to form a capacitor bank.
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore ESL contributes to part of the voltage sag. Use
a capacitor that has low ESL to obtain better transient
performance. Generally, using several capacitors
connected in parallel will have better transient performance
than using one single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, using a
mixed combination of electrolytic capacitor and ceramic
capacitor can also have better transient performance.
Output Capacitor Selection
The output capacitor and inductor form a low pass filter in
the buck topology. In steady state condition, the ripple
current flowing into/out of the capacitor results in ripple
voltage. The output voltage ripple (Vp-p) can be calculated
by the following equation.
VP−P
= LIR x ILOAD(MAX)
x
⎛
⎜ ESR
⎝
+
8
x
1
COUT
x fSW
⎞
⎟
⎠
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
VSAG = ΔILOAD x ESR
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on the SW pin when
high side MOSFET is turned on/off, this spike voltage on
SW may impact EMI performance in the system. In order
to enhance EMI performance, there are two methods to
suppress the spike voltage. One method is to place an R-
C snubber between SW and GND and locate them as close
as possible to the SW pin (see Figure 3). Another way is
adding a resistor in series with the bootstrap capacitor,
CBOOT, but this will decrease the driving capability to the
high side MOSFET. It is strongly recommended to reserve
the R-C snubber during PCB layout for EMI improvement.
Moreover, reducing the SW trace area and keeping the
main power in a small loop will be helpful for EMI
performance. For detailed PCB layout guideline, please
refer to the section on Layout Consideration.
VIN
4.5V to 23V
Chip Enable
REN*
CEN*
CSS
0.1µF
CIN
10µF x 2
2 VIN
BOOT 1 RBOOT*
RT8253A
7 EN
SW 3
CBOOT
0.1µF
Rs*
L
10µH
Cs*
8 SS
4, 9 (Exposed Pad)
GND
FB 5
COMP 6
RC CC
15k 3.3nF
VOUT
3.3V/3A
R1
31.25k
COUT
22µF x 2
R2
10k
CP
NC
Figure 3. Reference Circuit with Snubber and Enable Timing Control
DS8253A-02 March 2011
www.richtek.com
11
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