SPCA711A データシートの表示（PDF） - Unspecified

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SPCA711A

DIGITAL VIDEO ENCODER FOR VIDEOCD

Unspecified 

SPCA711A

Table 3. Configuration Register Settings

Mode Register Name

Set to 0

EFIELD

The VSYNC pin will output

normal vertical

synchronization signals.

PAL625

YCSWAP

PALSA

The 525-line operation will

be selected.

Do not swap Y and Cr/Cb

Sequence.

When the PAL625 register

is set to high, the PAL-

BDGHI mode is selected.

When the PAL625 register

is set to low, the NTSC

mode is selected.

Set to 1

The VSYNC pin will

output field signals.

Low at the VSYNC pin

for an even field, high for

odd field.

The 625-line operation

will be selected

Swap Y and Cr/Cb

sequence.

When the PAL625

register is set to high, the

PAL-Nc mode is

selected. When the

PAL625 register is set to

low, the PAL-M mode is

selected.

Comments

This is only used in the

master mode.

This is only used in the

master mode

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CLOCK TIMING

A clock signal with a frequency of twice the luminance sampling rate must be present at the CLK pin. All setup

and hold timing specifications are measured with respect to the rising edge of this signal.

PIXEL INPUT TIMING

! PIXEL SEQUENCE

Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs. By default, the input sequence for active

video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656. This pattern

begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER

mode). Cb and Cr order can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing. If the

pixel stream input to the SPCA711A is off by one CLK period, the SPCA711A can lock to the pixel stream by

setting the YCSWAP register. This will prevent Y and Cr/Cb pixels from swapping.

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