SPHE8200A データシートの表示（PDF） - Unspecified

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SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

1: Enable Chip Select 4 (default)

0: Disabled (CS4 becomes GPIO)

OE

OEB (ROM/FLASH output enable) function control

1: Enable OE function (default)

0: Disabled (OEB becomes GPIO)

l Y WE

WEB (FLASH/SRAM write enable) function control

tia G 1: Enable WEB function (default)

0: Disabled (WEB becomes GPIO)

n O CHRDY

IOCHRDY (ISA_IOCHRDY) function control

e L 1: Enable IOCHRDY input (i.e. output always tri-stated)

fid O C 0: Disabled (default)

n N IN pcmcia_IORW PCMCIA IOR/IOW select

o H 000: Disabled (default)

E 001: IOR from pin 19, IOW from pin 20

s C EC IS 010: IOR from pin 135, IOW from pin 136

011: IOR from pin 58, IOW from pin 59

lu T D Y 100: Available only at 256 pin package

np IC N L 101 to 111: Reserved

A pcmcia_WAIT bit 12-10 : PCMCIA_WAIT_B select

u N N 000: Disabled (default)

H O 001: PCMCIA_WAIT_B is from pin 21

S N C 010: PCMCIA_WAIT_B is from pin 61

U R E 011: PCMCIA_WAIT_B is from pin 129

S E S 100: PCMCIA_WAIT_B is from pin 138

r U 101: Available only at 256 pin package

o M 011 to 111: reserved

F & BOOT

RISC32 reset boot address

0: RISC32 boots from bfc0_0000 (internal ROM) (default)

1: RISC32 boots from 8000_0000 (SDRAM region)

LPT

LPT handshake signals (STROBE, ACK) select

00: Disabled (default)

01: LPT STROBE is from pin 62, LPT ACK is from pin 64

10: LPT STROBE is from pin 135, LPT ACK is from pin 136

11: Available only at 256 pin package

© Sunplus Technology Co., Ltd.

32

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

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