SPHE8200A データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

メーカー

SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

1: Swap UART0 and UART1 signals

0xbffe8050 sft_cfg3 (Audio interface and TV interface control)

Description

Pin MUX control register #3 (reference pin multiplex table for detailed information)

Attribute: RW

tial GY Bit-field

n O Reset

15 14

pc_SYNC

0

0

13 12

TELETEXT

0

0

11 10

9

SYNC

0

0

0

8

7

6

5

4

3

2

1

AUD LRCK AU4 AU3 AU2

EADC

0

1

1

1

1

1

0

0

fide OL C EDAC

nplus ICCoTnEACNHDNISLEYIN AU2

Su NN CH ON AU3

For S&U MER USE AU4

External ADC select

000: Disabled (default)

001: BCK is from pin 19, LRCK is from pin 20, DATA is from pin 21

010: BCK is from pin 58, LRCK is from pin 59, DATA is from pin 60

011: BCK is from pin 34, LRCK is from pin 35, DATA is from pin 37

100: BCK is from pin 130, LRCK is from pin 131, DATA is from pin 133

101: BCK is from pin 141, LRCK is from pin 143, DATA is from pin 144

110: Available only at 256 pin package

111: reserved

Audio DAC interface data #2 (AU_DATA[2]) function control

0: Disabled (AU_DATA[2] becomes GPIO)

1: Enable (default)

Audio DAC interface data #3 (AU_DATA[3]) function control

0: Disabled (AU_DATA[3] becomes GPIO)

1: Enable (default)

Audio DAC interface data #4 (AU_DATA[4]) function control

0: Disabled (AU_DATA[4] becomes GPIO)

1: Enable (default)

0

0

LRCK

Audio DAC interface LRCK function control

0: Disable

1: Enable (default)

AUD

Audio function

0: Disable

1: enable (default)

SYNC

H/V SYNC select

000: Disabled (default)

001: Reserved

010: Slave mode: HSYNC is from pin 146, VSYNC is from pin 148

011: Master mode: HSYNC is on pin 146, VSYNC is on pin 148

© Sunplus Technology Co., Ltd.

34

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

Share Link: