VRS700 データシートの表示（PDF） - Unspecified
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VRS700 Datasheet PDF : 45 Pages
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VRS700
VERSA
Datasheet Rev 1.3
Description of Peripherals
System Control Register
The System control Register serves the following
functions:
• Flag that shows Watch Dog Timer reset has
occurred.
• Controls the activation of the expanded RAM
Memory.
• Controls the ALE output.
The Table 10 shows the structure of the System
Control Register.
The WDR bit is a flag that indicates whether the Watch
Dog Timer has caused the system reset. When the
WDT is enabled, users should check the WDR bit
whenever an unpredicted reset occurs.
The OME bit allows the user to enable or disable the
on-chip expanded 3840 bytes of RAM. By default, after
reset, the expanded RAM memory is disabled
(OME=0). This bit must be set to 1 to activate the
expanded RAM memory.
The ALE bit controls the ALE output activity.
By default, the ALE pin is active. In applications where
the program is executed from the internal flash memory
of the VRS700, the ALE pin is usually of no use, so it is
advisable to inhibit the ALE output in order to reduce
the EMI generated by the device.
By default, the ALE pin is active and emits a signal of a
frequency of Fosc/6. Setting the ALE bit of the System
Control Register inhibits the ALE output.
TABLE 10: SYSTEM CONTROL REGISTER (SCONF) – SFR BFH
7
6
5
4
3
2
WDR
Unused
1
OME
0
ALEI
Bit Mnemonic Description
7
WDR
This is the Watch Dog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
6
Unused
-
5
Unused
-
4
Unused
-
3
Unused
-
2
Unused
-
1
OME
3840 bytes of on-chip enable bit
0
ALEI
ALE output inhibit bit, which is used to
reduce EMI.
Power Control Register
The VRS700 provides two power saving modes: Idle
and Power Down. These two modes serve to reduce
the power consumption of the device.
In Idle mode, the processor is stopped but the oscillator
is still running. The content of the RAM, I/O state and
SFR registers are maintained. Timer operation is
maintained, as well as the external interrupts.
This mode is useful for applications in which stopping
the processor to save power is required. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator of the VRS700 is
stopped. This means that all the peripherals are
disabled. The content of the RAM and the SFR
registers, however, is maintained.
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register (Table 11)
at address 87h.
TABLE 11: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6
5
4
3
2
Unused
1
RAMS1
0
RAMS0
Bit Mnemonic Description
7 SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6 Unused
-
5 Unused
-
4 Unused
-
3 GF1
General Purpose Flag
2 GF0
General Purpose Flag
1 PDOWN Power down mode control bit
0 IDLE
Idle mode control bit
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
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