AD9361
Data Sheet
CURRENT CONSUMPTION—VDD_INTERFACE
Table 2. VDD_INTERFACE = 1.2 V
Parameter
SLEEP MODE
1RX, 1TX, DDR
LTE10
Single Port
Dual Port
LTE20
Dual Port
2RX, 2TX, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
Dual Port
GSM
Dual Port
WiMAX 8.75
Dual Port
WiMAX 10
Single Port
TDD RX
TDD TX
FDD
WiMAX 20
Dual Port
FDD
Min
Typ
Max
Unit
Test Conditions/Comments
45
µA
Power applied, device disabled
2.9
mA
30.72 MHz data clock, CMOS
2.7
mA
15.36 MHz data clock, CMOS
5.2
mA
30.72 MHz data clock, CMOS
1.3
mA
7.68 MHz data clock, CMOS
4.6
mA
61.44 MHz data clock, CMOS
5.0
mA
30.72 MHz data clock, CMOS
8.2
mA
61.44 MHz data clock, CMOS
0.2
mA
1.08 MHz data clock, CMOS
3.3
mA
20 MHz data clock, CMOS
0.5
mA
22.4 MHz data clock, CMOS
3.6
mA
22.4 MHz data clock, CMOS
3.8
mA
44.8 MHz data clock, CMOS
6.7
mA
44.8 MHz data clock, CMOS
Table 3. VDD_INTERFACE = 1.8 V
Parameter
SLEEP MODE
1RX, 1TX, DDR
LTE10
Single Port
Dual Port
LTE20
Dual Port
2RX, 2TX, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
Dual Port
GSM
Dual Port
WiMAX 8.75
Dual Port
Min
Typ
Max
Unit
Test Conditions/Comments
84
μA
Power applied, device disabled
4.5
mA
30.72 MHz data clock, CMOS
4.1
mA
15.36 MHz data clock, CMOS
8.0
mA
30.72 MHz data clock, CMOS
2.0
mA
8.0
mA
7.5
mA
14.0
mA
0.3
mA
5.0
mA
Rev. F | Page 8 of 36
7.68 MHz data clock, CMOS
61.44 MHz data clock, CMOS
30.72 MHz data clock, CMOS
61.44 MHz data clock, CMOS
1.08 MHz data clock, CMOS
20 MHz data clock, CMOS