55LD019A-45-C-BWE データシートの表示（PDF） - Silicon Storage Technology
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55LD019A-45-C-BWE Datasheet PDF : 79 Pages
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ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
Data Sheet
TABLE 3-1: Pin Assignments (1 of 4)
Pin No.
Symbol
85-
100-TQFP VFBGA
Host Side Interface
A2
53
B2
A1
22
D9
A0
23
D8
D15
65
D3
D14
66
E2
D13
67
E3
D12
68
F2
D11
70
F3
D10
71
G1
D9
72
G2
D8
73
G3
D7
3
J9
D6
4
H10
D5
5
H9
D4
6
H8
D3
8
G9
D2
9
G8
D1
10
F10
D0
11
F9
DMACK
20
E8
DMARQ
14
F8
CS1FX#
24
C10
CS3FX#
52
B1
CSEL
56
C3
IORD#
IOWR#
IOCS16#
INTRQ
PDIAG#
DASP#
RESET#
19
E9
57
D1
55
C2
21
D10
54
C1
75
H2
1
K10
84- Pin
TFBGA Type
J8
G3
I
H1
F8
E10
E9
E8
D10
D9
C10
D8
I/O
C3
C4
B2
D4
C2
D3
C1
D2
G2
I
E3
O
H2
K9
I
J10
I
F1
I
H9
H8
O
G1
O
J9 I/O
B10 I/O
A2
I
I/O
Type1 Name and Functions
I1Z A[2:0] are used to select one of eight registers in the Task File.
I1Z/O2 D[15:0] Data bus
I2U
O1
I2Z
I1U
I2Z
O2
O1
I1U/O1
I1U/O6
I2U
DMA Acknowledge - input from host
DMA Request to host
CS1FX# is the chip select for the task file registers
CS3FX# is used to select the alternate status register and the
Device Control register.
This internally pulled-up signal is used to configure this device
as a Master or a Slave. When this pin is grounded, this device
is configured as a Master. When the pin is open, this device is
configured as a Slave. The pin setting should remain the same
from Power-on to Power-down.
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the chip.
The I/O Write strobe pulse is used to clock I/O data into the
chip.
This output signal is asserted low when the device is indicating
a word data transfer cycle.
This signal is the active high Interrupt Request to the host.
The Pass Diagnostic signal in the Master/Slave handshake
protocol.
The Drive Active/Slave Present signal in the Master/Slave
handshake protocol.
This input pin is the active low hardware reset from the host.
©2006 Silicon Storage Technology, Inc.
10
S71241-04-000
12/06
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