AD5372 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD5372

32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC

Analog Devices 

GENERAL DESCRIPTION

The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead

LQFP and LFCSP packages. The devices provide buffered

voltage outputs with a nominal span of 4× the reference voltage.

The gain and offset of each DAC can be independently trimmed

to remove errors. For even greater flexibility, the device is divided

into four groups of eight DACs. Two offset DACs allow the

output range of the groups to be altered. Group 0 can be adjusted

by Offset DAC 0, and Group 1 to Group 3 can be adjusted by

Offset DAC 1.

The AD5372/AD5373 offer guaranteed operation over a wide

supply range: VSS from −16.5 V to −4.5 V and VDD from 9 V to

16.5 V. The output amplifier headroom requirement is 1.4 V

operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model

Resolution (Bits) Nominal Output Span

AD5360

16

4 × VREF (20 V)

AD5361

14

4 × VREF (20 V)

AD5362

16

4 × VREF (20 V)

AD5363

14

4 × VREF (20 V)

AD5370

16

4 × VREF (12 V)

AD5371

14

4 × VREF (12 V)

AD5372

16

4 × VREF (12 V)

AD5373

14

4 × VREF (12 V)

AD5378

14

±8.75 V

AD5379

14

±8.75 V

AD5372/AD5373

The AD5372/AD5373 have a high speed serial interface that is

compatible with SPI, QSPI™, MICROWIRE™, and DSP inter-

face standards and can handle clock speeds of up to 50 MHz.

The DAC registers are updated on reception of new data. All

the outputs can be updated simultaneously by taking the LDAC

input low. Each channel has a programmable gain and an offset

adjust register.

Each DAC output is gained and buffered on chip with respect

to an external SIGGNDx input. The DAC outputs can also be

switched to SIGGNDx via the CLR pin.

Output Channels

16

16

8

8

40

40

32

32

32

40

Linearity Error (LSB)

±4

±1

±4

±1

±4

±1

±4

±1

±3

±3

Rev. C | Page 3 of 28

Share Link: