AD7440BRT-R2 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD7440BRT-R2

Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23

Analog Devices 

AD7440/AD7450A

Parameter

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time2

Throughput Rate

POWER REQUIREMENTS

VDD

IDD 8

Normal Mode (Static)

Normal Mode (Operational)

Full Power-Down Mode

Power Dissipation

Normal Mode (Operational)

Full Power-Down Mode

Test Conditions/Comments

888 ns with an 18 MHz SCLK

Sine wave input

Step input

Range: 3 V + 20%/–10%; 5 V ± 5%

SCLK on or off

VDD = 4.75 V to 5.25 V

VDD = 2.7 V to 3.6 V

SCLK on or off

VDD = 5 V, 1.55 mW typ for 100 kSPS9

VDD = 3 V, 0.6 mW typ for 100 kSPS9

VDD = 5 V, SCLK on or off

VDD = 3 V, SCLK on or off

B Version

16

200

290

1

2.7/5.25

0.5

1.95

1.45

1

9.25

4

5

3

Unit

SCLK cycles

ns max

ns max

MSPS max

V min/V max

mA typ

mA max

mA max

μA max

mW max

mW max

μW max

μW max

1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.

2 See the Terminology section.

3 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an

incorrect result.

4 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.

5 The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.

6 The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.

7 Guaranteed by characterization.

8 Measured with a midscale dc input.

9 See the Power vs. Throughput section.

Rev. C | Page 4 of 28

Share Link: