AD7450A データシートの表示（PDF） - Analog Devices
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AD7450A Datasheet PDF : 28 Pages
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AD7440/AD7450A
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. See Figure 2, Figure 3, and the Serial Interface section.
Table 3. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS,
VREF = 2.5 V; VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Parameter Limit at TMIN, TMAX
Unit
Description
fSCLK 2
10
kHz min
18
MHz max
tCONVERT
16 × tSCLK
tSCLK = 1/fSCLK
888
ns max
tQUIET
60
ns min
Minimum quiet time between the end of a serial read and the next falling edge of CS
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS falling edge to SCLK falling edge setup time
t3 3
20
ns max
Delay from CS falling edge until SDATA three-state disabled
t43
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK high pulse width
t6
0.4 tSCLK
ns min
SCLK low pulse width
t7
10
ns min
SCLK edge to data valid hold time
t8 4
10
ns min
SCLK falling edge to SDATA three-state enabled
35
ns max
SCLK falling edge to SDATA three-state enabled
t5
POWER-UP
1
μs max
Power-up time from full power-down
1 Common-mode voltage.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V or 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power-Up Time section.
CS
t2
SCLK
t3
SDATA
CS
t2
SCLK
t3
SDATA
t1
1
2
3
t4
0
0
0
0
4 LEADING ZEROS
t5
4
tCONVERT
5
t7
DB11 DB10
B
13
14
t6
15
t8
DB2
DB1
DB0
16
tQUIET
THREE-STATE
Figure 2. AD7450A Serial Interface Timing Diagram
t1
tCONVERT
t5
B
1
2
3
4
5
13
14
15
16
0
0
t4
t7
0
0
DB9
DB8
t6
t8
DB0
0
0
tQUIET
4 LEADING ZEROS
2 TRAILING ZEROS THREE-STATE
Figure 3. AD7440 Serial Interface Timing Diagram
Rev. C | Page 7 of 28
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