AD7451ARMZ データシートの表示（PDF） - Analog Devices
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AD7451ARMZ Datasheet PDF : 24 Pages
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AD7441/AD7451
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time1
Throughput Rate
POWER REQUIREMENTS
VDD
IDD6, 7
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
888 ns with an 18 MHz SCLK
Sine wave input
Step input
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
VDD = 5 V; 1.55 mW typ for 100 ksps6
VDD = 3 V; 0.6 mW typ for 100 ksps6
VDD = 5 V; SCLK on or off
VDD = 3 V; SCLK on or off
B Version
16
250
290
1
2.7/5.25
0.5
1.95
1.45
1
9.25
4
5
3
Unit
SCLK cycles
ns max
ns max
MSPS max
V min/max
mA typ
mA max
mA max
μA max
mW max
mW max
μW max
μW max
1 See the Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.
4 The AD7441 is functional with a reference input in the range 100 mV to VDD.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
Rev. D | Page 6 of 24
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