AD5412ACPZ-REEL7 データシートの表示（PDF） - Analog Devices
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AD5412ACPZ-REEL7
Analog Devices
AD5412ACPZ-REEL7 Datasheet PDF : 44 Pages
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Data Sheet
AD5412/AD5422
Parameter1, 2, 3
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
Limit at TMIN, TMAX
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = capacitive load on SDO output.
Timing Diagrams
SCLK
LATCH
SDIN
1
2
t2
t1
24
t3
t4
t5
t7
t6
DB23
t8
DB0
CLEAR
IOUT, VOUT
t9
t10
Figure 2. Write Mode Timing Diagram
Rev. O | Page 11 of 44
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