AD6643 データシートの表示（PDF） - Analog Devices

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AD6643

Dual IF Receiver

Analog Devices 

Data Sheet

When the NSR block is disabled, the ADC data is provided directly

to the output at a resolution of 11 bits. The AD6643 can achieve

up to 66.5 dBFS SNR for the entire Nyquist bandwidth when

operated in this mode. This allows the AD6643 to be used in

telecommunication applications such as a digital predistortion

observation path where wider bandwidths are required.

After digital signal processing, multiplexed output data is

routed into two 11-bit output ports such that the maximum

data rate is 400 Mbps (DDR). These outputs are LVDS and

support ANSI-644 levels.

The AD6643 receiver digitizes a wide spectrum of IF frequencies.

Each receiver is designed for simultaneous reception of a separate

antenna. This IF sampling architecture greatly reduces compo-

nent cost and complexity compared with traditional analog

techniques or less integrated digital methods.

Flexible power-down options allow significant power savings.

Programming for device setup and control is accomplished

using a 3-wire SPI-compatible serial interface with numerous

modes to support board level system testing.

AD6643

The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead,

9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is

specified over the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Two ADCs are contained in a small, space-saving,

9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package.

2. Pin selectable noise shaping requantizer (NSR) function

that allows for improved SNR within a reduced bandwidth

of up to 60 MHz at 185 MSPS.

3. LVDS digital output interface configured for low cost

FPGA families.

4. Operation from a single 1.8 V supply.

5. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary or twos complement), NSR, power-down,

test modes, and voltage reference mode.

6. On-chip integer 1-to-8 input clock divider and multichip

sync function to support a wide range of clocking schemes

and multichannel subsystems.

Rev. C | Page 3 of 40

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