AD6643 データシートの表示（PDF） - Analog Devices
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AD6643 Datasheet PDF : 40 Pages
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AD6643
Data Sheet
Parameter1
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS)
CROSSTALK2
FULL POWER BANDWIDTH3
AD6643-200
AD6643-250
Temperature Min
Typ
Max
Min
Typ
Max
Unit
25°C
92
90
dBc
25°C
91
88
dBc
Full
80
dBc
25°C
88
86
dBc
25°C
88
85
dBc
Full
79
dBc
25°C
84
85
dBc
25°C
−94
−94
dBc
25°C
−94
−93
dBc
Full
−80
dBc
25°C
−95
−92
dBc
25°C
−94
−92
dBc
Full
−80
dBc
25°C
−93
−88
dBc
25°C
88
Full
95
25°C
1000
88
dBc
95
dB
1000
MHz
1 For a complete set of definitions, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.
2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
3 Full power bandwidth is the bandwidth for the ADC inputs at which the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,
DCS enabled, default SPI, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
Input Current Level
High
Low
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
Input Voltage Level
High
Low
Temperature Min
Typ
Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.3
3.6
Full
AGND
AVDD
Full
0.9
1.4
Full
10
22
Full
−22
−10
Full
4
Full
8
10
12
CMOS/LVDS
Full
0.9
Full
AGND
AVDD
Full
1.2
Full
AGND
AVDD
0.6
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
Rev. C | Page 6 of 40
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