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AD5383 データシートの表示(PDF) - Analog Devices

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AD5383 Datasheet PDF : 40 Pages
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AD5383
GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit
denseDAC® available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference; an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring; and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
features
Double-buffered parallel interface with a 20 ns WR
pulse width.
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial
interface with interface speeds in excess of 30 MHz.
I2C-compatible interface that supports a 400 kHz data
transfer rate.
Data Sheet
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated independently
or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust register
that allows the user to fully calibrate any DAC channel. With
boost off, power consumption is typically 0.25 mA/channel.
Rev. D | Page 4 of 40

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