AD7829-1 データシートの表示（PDF） - Analog Devices

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AD7829-1

3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC

Analog Devices 

A suggestion is to tie CONVST to VDD or DGND through a

pull-up or pull-down resistor. A rising edge on the CONVST

pin causes the AD7829-1 to fully power up. For applications

where power consumption is of concern, the automatic power-

down at the end of a conversion should be used to improve

power performance (see the Power vs. Throughput section).

If the AD7829-1 is operated outside normal VDD limits (for

example, a brown-out), it may take two conversions to reset the

part once the correct VDD has been established.

SUPPLY

4.5V TO 5.5V

10µF

0.1µF

2.5V

AD780

PARALLEL

INTERFACE

1.25V TO

3.75V INPUT

VDD

VIN1

VREF

VMID

DB0 TO DB7

EOC

VIN2 AD7829-1

RD

CS

VIN8

AGND

CONVST

A0

A1

DGND

A2

µC/µP

Figure 7. Typical Connection Diagram

ADC TRANSFER FUNCTION

The output coding of the AD7829-1 is straight binary. The

designed code transitions occur at successive integer LSB values

(that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to

VREF/256 (VDD = 5 V), or the LSB size is equal to (0.8 VREF)/256

(VDD = 3 V). The ideal transfer characteristic for the AD7829-1

is shown in Figure 8.

11111111

111...110

(VDD = 5V)

1LSB = VREF/256

111...000

10000000

000...111

(VDD = 3V)

1LSB = 0.8VREF/256

000...010

000...001

00000000

1LSB

VMID

(VDD = 5V) VMID – 1.25V

(VDD = 3V) VMID – 1V

VMID + 1.25V – 1LSB

VMID + 1V – 1LSB

ANALOG INPUT VOLTAGE

Figure 8. Transfer Characteristic

AD7829-1

ANALOG INPUT

The AD7829-1 has eight input channels. Each input channel has

an input span of 2.5 V or 2.0 V, depending on the supply voltage

(VDD). This input span is automatically set up by an on-chip

“VDD detector” circuit. A 5 V operation of the ADCs is detected

when VDD exceeds 4.1 V, and a 3 V operation is detected when

VDD falls below 3.8 V. This circuit also possesses a degree of

glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to

60 ns wide does not trip the VDD detector.

The VMID pin is used to center this input span anywhere in the

range of AGND to VDD. If no input voltage is applied to VMID,

the default input range is AGND to 2.0 V (VDD = 3 V ± 10%),

that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V ± 10%),

that is, centered about 1.25 V. When using the default input range,

the VMID pin can be left unconnected; or, in some cases, it can be

decoupled to AGND with a 0.1 μF capacitor.

If, however, an external VMID is applied, the analog input range

is from VMID − 1.0 V to VMID + 1.0 V (VDD = 3 V ± 10%), or from

VMID − 1.25 V to VMID + 1.25 V (VDD = 5 V ± 10%).

The range of values of VMID that can be applied depends on the

value of VDD. For VDD = 3 V ± 10%, the range of values that can

be applied to VMID is from 1.0 V to VDD − 1.0 V and is 1.25 V to

VDD − 1.25 V when VDD = 5 V ± 10%. Table 5 shows the relevant

ranges of VMID and the input span for various values of VDD.

Figure 9 illustrates the input signal range available with various

values of VMID.

Table 5.

VMID

VDD Internal

5.5 1.25

5.0 1.25

4.5 1.25

3.3 1.00

3.0 1.00

2.7 1.00

VMID Ext

Maximum

4.25

3.75

3.25

2.3

2.0

1.7

VIN Span

3.0 to 5.5

2.5 to 5.0

2.0 to 4.5

1.3 to 3.3

1.0 to 3.0

0.7 to 2.7

VMID Ext

Minimum

1.25

1.25

1.25

1.00

1.00

1.00

VIN Span

0 to 2.5

0 to 2.5

0 to 2.5

0 to 2.0

0 to 2.0

0 to 2.0

Rev. 0 | Page 11 of 20

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