AD7476 データシートの表示（PDF） - Analog Devices
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AD7476 Datasheet PDF : 20 Pages
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(A Version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise
AD7476–SPECIFICATIONS1noted; S and B Versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS,
unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1, 2 B Version1, 2 S Version1, 2 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)3 69
70
Signal-to-Noise Ratio (SNR)3
70
Total Harmonic Distortion (THD)3
–80
Peak Harmonic or Spurious Noise (SFDR)3 –82
Intermodulation Distortion (IMD)3
Second-Order Terms
–78
Third-Order Terms
–78
Aperture Delay
10
Aperture Jitter
30
Full Power Bandwidth
6.5
DC ACCURACY
Resolution
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
Gain Error3
12
±1
± 0.75
± 0.5
± 0.5
70
71.5
71
72.5
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 1.5
± 1.5
69
70
70
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
±2
±2
dB min
dB min
dB typ
dB min
dB typ
dB typ
dB typ
fIN = 100 kHz Sine Wave
B Version, VDD = 2.4 V to 5.25 V
TA = 25°C
B Version, VDD = 2.4 V to 5.25 V
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B Versions, VDD = (2.35 V to 3.6 V)4;
A Version, VDD = (2.7 V to 3.6 V)
Guaranteed No Missed Codes to 12 Bits
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
±1
30
0 to VDD
±1
30
0 to VDD
±1
30
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
2.4
2.4
1.8
1.8
0.4
0.4
0.8
0.8
±1
±1
±1
±1
10
10
VDD – 0.2
0.4
VDD – 0.2
0.4
± 10
± 10
10
10
Straight (Natural) Binary
2.4
1.8
0.4
0.8
±1
±1
10
VDD – 0.2
0.4
± 10
10
V min
V min
V max
V max
µA max
µA typ
pF max
V min
V max
µA max
pF max
VDD = 2.35 V
VDD = 3 V
VDD = 5 V
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 µA; VDD = 2.35 V to 5.25 V
ISINK = 200 µA
CONVERSION RATE
Conversion Time
0.8
1.33
1.33
µs max
16 SCLK Cycles
Track-and-Hold Acquisition Time
500
500
500
ns max
Full-Scale Step Input
350
400
400
ns max
Sine Wave Input ≤100 kHz
Throughput Rate
1000
600
600
kSPS max See Serial Interface Section
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation7
Normal Mode (Operational)
Full Power-Down
2.35/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
3
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
V min/max
mA typ
mA typ
mA max
mA max
µA max
µA max
Digital I/Ps = 0 V or VDD
VDD = 4.75 V to 5.25 V. SCLK On or Off
VDD = 2.35 V to 3.6 V. SCLK On or Off
VDD = 4.75 V to 5.25 V; fSAMPLE = fSAMPLEMAX6
VDD = 2.35 V to 3.6 V; fSAMPLE = fSAMPLEMAX6
SCLK Off
SCLK On
mW max
mW max
µW max
µW max
VDD = 5 V; fSAMPLE = fSAMPLEMAX6
VDD = 3 V; fSAMPLE = fSAMPLEMAX6
VDD = 5 V; SCLK Off
VDD = 3 V; SCLK Off
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2Operational from VDD = 2.0 V.
3See Terminology section.
4Maximum B, S version specifications apply as typical figures when V DD = 5.25 V.
5Guaranteed by characterization.
6A Version: fSAMPLEMAX = 1 MSPS; B, S Versions: fSAMPLEMAX = 600 kSPS.
7See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. D
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