AD7476 データシートの表示（PDF） - Analog Devices
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AD7476 Datasheet PDF : 20 Pages
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AD7476/AD7477/AD7478
TIMING SPECIFICATIONS1, 2
(VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
AD7476/AD7477/AD7478
3 V3
5 V3
Unit
Description
fSCLK4
tCONVERT
tQUIET
t1
t2
t35
t45
t5
t6
t7
t86
tPOWER-UP7
10
20
12
16 × tSCLK
50
10
10
20
40
70
0.4 × tSCLK
0.4 × tSCLK
10
10
25
1
10
20
12
16 × tSCLK
50
10
10
20
20
20
0.4 × tSCLK
0.4 × tSCLK
10
10
25
1
kHz min
MHz max
MHz max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
A Version
B Version
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum CS Pulsewidth
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge, A Version
Data Access Time after SCLK Falling Edge, B Version
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
NOTES
1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.
33 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.
4Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time
of the part and is independent of the bus loading.
7See Power-Up Time section.
Specifications subject to change without notice.
200A
IOL
TO OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
REV. D
–5–
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