AD5541AARMZ-REEL7 データシートの表示（PDF） - Analog Devices
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AD5541AARMZ-REEL7 Datasheet PDF : 20 Pages
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Data Sheet
AD5541A
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, −40°C < TA < +105°C, unless otherwise
noted.
Table 4.
Parameter1,2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
Limit at
1.8 ≤ VLOGIC ≤ 2.7 V
14
70
35
35
5
5
5
10
35
5
5
20
10
15
Limit at
2.7 V ≤ VLOGIC ≤ 5.5 V
50
20
10
10
5
5
5
5
10
4
5
20
10
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3 V, VINL = 0 V)
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
1 Guaranteed by design and characterization. Not production tested.
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK
CS
DIN
LDAC
t6
t4
t12
t8
t9
DB15
t1
t2
t3
t5
t7
t11
t10
Figure 3. Timing Diagram
Rev. B | Page 5 of 20
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