ANX9011 データシートの表示（PDF） - Unspecified
部品番号
コンポーネント説明
メーカー
ANX9011 Datasheet PDF : 2 Pages
| |||
Product Brief
ANX9030
FEATURES
HDMI Transmitter
z HDMI 1.2 compliant transmitter with HDCP
z Supports pixel rates beyond 165 Mpix/second
z Low power consumption of 300 mW typical
for 720P or 1080I
z Supports One Bit Audio (DSD, SACD)
z Pin compatible with SiI9030
z Built‐in video pattern generator and audio
tone generator for system self‐test
z Firmware programmable output swing and
pre‐emphasis
z HDCP 1.2 compliant with internal keys
z Backward compatible with DVI 1.0 standard
z Flexible 24‐bit video pixel input interface
z Supports 12/24‐bit modes, 4:2:2, DDR, etc.
z Flexible digital audio interface
z Supports S/PDIF, 8‐ch I2S, 6‐ch 1‐bit audio
z Fully integrated HDCP authentication hardware
z Automatic arbitration between host and DDC
access through I2C port
z Software‐controlled power management
z 80‐lead TQFP lead‐free package
The ANX9030 is a high‐performance, High Defini‐
tion Media Interface (HDMI) transmitter chip with
an advanced feature set offered only by Analogix
Semiconductor.
The ANX9030 is pin‐compatible with the SiI9030 yet
offers additional features and functionality and
lower power operation. It includes HDCP 1.2
(High‐Bandwidth Digital Content Protection) cir‐
cuitry with internal memory to store a unique HDCP
device key.
The device directly interfaces to the HDMI output
connector of an HDMI‐enabled digital video source,
such as a digital set‐top box, DVD player, or inte‐
grated Audio/Video receiver. It also includes other
HDMI connector functions such as the I2C interface
for the DDC (Display Data Channel) and the Hot
Plug Detection input.
The ANX9030 accepts digital video and audio in
many commonly used data formats, sample rates,
and bit resolutions. Video, audio, auxiliary, and con‐
trol data is packetized according to HDMI standards,
making the ANX9030 fully compatible with HDMI
receivers such as the ANX9011 and ANX9021.
The ANX9030 is offered in an 80‐lead TQFP package.
DATA_CLK
D [23:0]
VSYNC
HSYNC
DE
S C K/SAU D _C LK
S D O /S A U D 0
S D 1/S A U D 1
S D 2/S A U D 2
S D 3/S A U D 3
W S/SAU D 4
M C LK
S PD IF/SAU D 5
CSDA
CSCL
IN TP
PLL
V ideo D ata C apture
DE Gen
B IS T
4:2:2 to 4:4:4
Y C bC r to R G B
A udio D ata C apture
B IS T
I2C
S lave
A uxiliary
Packet Gen
Block Diagram
HDCP Key
EPROM
HDCP
A uthorization
& E ncryption
TMDS
Tx
C onfiguration
R egisters
D D C B ridge
DDC
M aster
TX 0[P ,N ]
TX 1[P ,N ]
TX 2[P ,N ]
TX C [P ,N ]
R _BIAS
HPD
DSCL
DSDA
August 2006
Copyright © 2006 Analogix Semiconductor, Inc
3211 Scott Blvd., Suite 100, Santa Clara, CA 95054, USA
Product Brief
Share Link: 