PIC32MZ2048ECG100 データシートの表示（PDF） - Microchip Technology
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PIC32MZ2048ECG100
Microchip Technology
PIC32MZ2048ECG100 Datasheet PDF : 650 Pages
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PIC32MZ Embedded Connectivity (EC) Family
Device Pin Tables
TABLE 3: PIN NAMES FOR 64-PIN DEVICES
64-PIN QFN(4) AND TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)064
PIC32MZ1024EC(G/H/M)064
PIC32MZ1024EC(E/F/K)064
PIC32MZ2048EC(G/H/M)064
M
64
1
QFN(4)
64
1
TQFP
Pin #
Full Pin Name
Pin #
Full Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
AN17/ETXEN/RPE5/PMD5/RE5
33 VBUS
AN16/ETXD0/PMD6/RE6
34 VUSB3V3
AN15/ETXD1/PMD7/RE7
35 VSS
AN14/C1IND/RPG6/SCK2/PMA5/RG6
36 D-
AN13/C1INC/RPG7/SDA4/PMA4/RG7
37 D+
AN12/C2IND/RPG8/SCL4/PMA3/RG8
38 USBID/RPF3/RF3
VSS
39 VDD
VDD
40 VSS
MCLR
41 RPF4/SDA5/PMA9/RF4
AN11/C2INC/RPG9/PMA2/RG9
42 RPF5/SCL5/PMA8/RF5
AN45/C1INA/RPB5/RB5
43 AERXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
AN4/C1INB/RB4
44 ECOL/RPD10/SCL1/SCK4/RD10
AN3/C2INA/RPB3/RB3
45 AERXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
AN2/C2INB/RPB2/RB2
46 AERXD1/ETXD3/RPD0/RTCC/INT0/RD0
PGEC1/VREF-/CVREF-/AN1/RPB1/RB1
47 SOSCI/RPC13/RC13
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
48 SOSCO/RPC14/T1CK/RC14
PGEC2/AN46/RPB6/RB6
49 EMDIO/AEMDIO/RPD1/SCK1/RD1
PGED2/AN47/RPB7/RB7
50 ETXERR/AETXEN/RPD2/SDA3/RD2
AVDD
51 AERXERR/ETXCLK/RPD3/SCL3/RD3
AVss
52 SQICS0/RPD4/PMWR/RD4
AN48/RPB8/PMA10/RB8
53 SQICS1/RPD5/PMRD/RD5
AN49/RPB9/PMA7/RB9
54 VDD
TMS/CVREFOUT/AN5/RPB10/PMA13/RB10
55 VSS
TDO/AN6/PMA12/RB11
56 ERXD3/AETXD1/RPF0/RF0
VSS
57 TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
VDD
58 TRD0/SQID0/ERXD1/PMD0/RE0
TCK/AN7/PMA11/RB12
59 VSS
TDI/AN8/RB13
60 VDD
AN9/RPB14/SCK3/PMA1/RB14
61 TRD1/SQID1/ERXD0/PMD1/RE1
AN10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15
62 TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
OSCI/CLKI/RC12
63 TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
OSCO/CLKO/RC15
64 AN18/ERXERR/PMD4/RE4
1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001191B-page 4
Preliminary
2013 Microchip Technology Inc.
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