SC14480 データシートの表示（PDF） - Unspecified

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SC14480

1.8V Single Chip for DECT

Unspecified 

5.1 POWER-ON STATUS

The source of the power-on request can be read in the

BAT_STATUS_REG. PON_STS indicated the PON pin

was pressed, CHARGE_STS that a charger was con-

nected and VBAT3_STS that a rising edge on VBAT

occurred. The PON and CHARGE status bits are set

on a positive level and must be reset by writing a ‘0’ to

the registers. The status bits remain set as long as the

“pon” and “charge” conditions are valid.

P1.6, "pon"

S/R FF

PON_STS

PON

>10 ms

set

reset

Reset

OR write 0

270k

"charge"

CHARGE

Charge filter

S/R FF

set

CHARGE_STS

Hold 10ms

reset

Reset

P1.7

270k

~30ms ~200ms

OR write 0

fidential VBAT

Rising-edge

Detection

wait for 30ms +

keep for 200ms

"vbat_ok"

S/R FF

set

reset

VBAT3_STS

Reset

OR write 0

BAT_STATUS_REG

"new_bat"

August 29, 2007

Figure 14 Wake-up status circuit

n 5.2 BANDGAP REFERENCE

o The SC14480A5M, SC14480A2M6 has a bandgap

C register which is used by the analog codec front-end,

Radio frontend Battery management circuitry and ADC

as reference voltage.

The BANDGAP_REG has reset value 0xF, resulting in

an initial VDD/AVD voltage of 1.8V -0% +10%. This

voltage can be tuned in production to 1.8V with

BANDGAP_REG bits 3-0 to an accuracy better than

1%.

If VDD/AVDF is trimmed to 1%, VDDIO is 2% accurate.

The trimmed value written to BANDGAP_REG can be

saved by the CR16Cplus in the external EEPROM and

restored in the BANDGAP_REG register at system

startup.

See BANDGAP_REG (0xFF4810) (table 77, page 151)

for a registers on how to trim the voltages.

The BANDGAP_REG is only reset by a hardware reset

(RSTn)

© 2008-2009 SiTel Semiconductor

29

Version: January 21, 2009 v1.0

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