SC14480 データシートの表示（PDF） - Unspecified
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SC14480 Datasheet PDF : 259 Pages
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Table 1: Pin Description
PIN NAME
TYPE
Drive
(mA)
Reset
state
(Note 2)
DESCRIPTION
CHARGE_CTRL
A1
1
O-0
ANALOG output. Charge control pin. Supplied by VBAT
Debug interface
JTAG
DIOD-BP
8
I-PU
INPUT/OUTPUT. INPUT/OUTPUT. JTAG-SDI+ one wire inter-
face with opendrain. An external 1k pull-up resistor must be
present on the board for debugging.(see also Figure 83)
Default hot insertion is enabled; if JTAG pin pulled low after
reset, the JTAG-SDI is enabled and consumes power.
DEBUG_REG[CR16_DBGM] either allows ROM patching or
JTAG port. Refer to register description. Disabling the JTAG-SDI
port is possible if this pin is high during reset or by writing to
TEST__REG[_SDI] = ‘1’.
Interrupts
I-PU INPUT. 3 general purpose interrupts with rising/falling edge or
high/low levels. All inputs generate a KEYB_INT.
INT8
DI
INT8 is connected to P1[3]
INT7
DI / DI-BP
INT7 is connected to P1[2] or P2[7]
INT6
DI / DI-BP
INT6 is connected to P1[1] or P2[6]
ential INT5-INT0
DI
O-1
I-PD
I-PD
I-PU
I-PU
I-PU
INPUT. 6 Keyboard input interrupts requests with or without
debounce timer and programmable rising/falling edges. All inputs
generate a KEYB_INT.
INT5 is connected to P1[5]
INT4 is connected to P1[4]
INT3 is connected to P1[3]
INT2 is connected to P1[2]
INT1 is connected to P1[1]
INT0 is connected to P1[0]
SPI Interface
fid SPI_CLK
DO-BP
8
I-PU INPUT/OUTPUT. Clock
SPI_DI
DI-BP
I-PU INPUT. Data input
n SPI_DO
DO-BP
8
I-PU OUTPUT. Data output
SPI_EN
DI-BP
I-PU INPUT. Clock enable
o SPI2 Interface (Only on KGD and 100 pins device, not tested unless commercially discussed)
C SPI2_DI
DIO-BP
8
I-PU INPUT/OUTPUT port with selectable pull up/down resistor.
8
I-PU INPUT. SPI2 Data input
SPI2_DO
DIO-BP
8
8
I-PU
I-PU
INPUT/OUTPUT port with selectable pull up/down resistor.
OUTPUT. SPI2 Data output
SPI2_CLK
DIO-BP
8
8
I-PU
I-PU
INPUT/OUTPUT port with selectable pull up/down resistor.
INPUT/OUTPUT. SPI2 Clock
SPI2_EN
DIO-BP
8
8
I-PU
I-PU
INPUT/OUTPUT port with selectable pull up/down resistor.
INPUT. SPI2 Clock enable
ACCESS bus 1 Interface
SDA1
DIO-BP/
8
DIOD-BP
I-PU
INPUT / OUTPUT. ACCESS bus 1 Data with programmable
Push-pull or open drain
SCL1
DIO-BP/
8
DIOD-BP
I-PU
INPUT / OUTPUT. ACCESS bus 1 Clock with programmable
Push-pull or open drain. In open drain mode, SCL is monitored to
support bit stretching by a slave
ACCESS bus 2 Interface
SDA2
DIO-BP/
8
DIOD-BP
I-PU
INPUT / OUTPUT. ACCESS bus 2 Data with programmable
Push-pull or open drain
© 2008-2009 SiTel Semiconductor
7
Version: January 21, 2009 v1.0
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