SC14480A5MXXXXMDC データシートの表示（PDF） - Unspecified

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SC14480A5MXXXXMDC

1.8V Single Chip for DECT

Unspecified 

Table 1: Pin Description

PIN NAME

TYPE

Drive

(mA)

Reset

state

(Note 2)

DESCRIPTION

SCL2

DIO-BP/

8

DIOD-BP

I-PU

INPUT / OUTPUT. ACCESS bus 2 Clock with programmable

Push-pull or open drain. In open drain mode, SCL is monitored to

support bit stretching by a slave

UART Interface

UTX

DO-BP

8

I-PU OUTPUT. UART transmit data

URX

DI-BP

8

I-PU INPUT. UART receive data

Radio transceiver

RF_RXp

A9

-

I

RF Receiver input. Must be AC coupled

RF_RXn

A9

-

I

VSS_LNA

A9

-

I

LNA Ground

RF_TXp

RX_TXn

A10

-

A10

-

O

RF PA driver (open drain) outputs. Must be connected to

O

VDD_PADR by external matching circuit.

VDD_PADR

A10

-

O

Internally regulated power supply for the PA driver matching cir-

VSS_PADR

A10

-

I

REF_RES

A7

-

O

tial RFP0

D2

8

Hi-Z

RFP0n

D2

8

Hi-Z

RFP1

D2

8

Hi-Z

n RFP2

D2

8

Hi-Z

e RFP3

D2

8

Hi-Z

fid RFP4

D2

8

Hi-Z

Internal Baseband RF interface

(for monitoring/debugging purposes only)

n LE

DIO

2

I-PU

o SK

DIO

2

I-PU

C SIO

DIO

1/2

I-PD

cuit

PA driver matching circuit Ground

Connection for bias resistor to ground (56kΩ). For stability the

maximum paracitic load on this pin may not exceed 10 pF.

Digital outputs supplied with internal RF LDOs. (1.7V)

If the RF LDOs are not enabled, the output of these port can not

be used. Refer to Table 282 on page 225

For more information, refer to chapter “Microwire”

INPUT/OUTPUT. Microwire latch enable

INPUT/OUTPUT. Microwire clock

INPUT/OUTPUT. Microwire data

TDOD

DIO

1/2

I-PD INPUT/OUTPUT. Baseband Transmit Digital BMC Data.

RDI

DIO

8

O-1

INPUT/OUTPUT. Baseband Receive Data

CLASSD power amplifier

PAOUTp

PAOUTn

DOPD

DOPD

500

O-0

OUTPUT. CLASSD positive and negative output to 4 ohm loud-

(5k fixed speaker. These pin can be configured as general purpose out-

pull down) puts, but this will result is an extra static DC current, so this not

O-0

recommended in portable applications. (see DC characteristics

(5k fixed and (Note 5).

pull down) PAOUTp and PAOUTn are forced to VSSPA if

VDDPA > 3.3V ... 3.45V (trimmed BANDGAP_REG: AVD =

1.8V)

VDDPA > 3.15V ... 3.6V (BANDGAP_REG = 0x8) (Note 6)

VDDPA

A1

-

Supply voltage CLASSD audio amplifier up to 3.45V

VSSPA

-

-

Ground for CLASSD power amplifier, connected to GND plane

Audio Codec

LSRp or

AGND

A1

-

O

OUTPUT. Positive loudspeaker output

OUTPUT. Buffered analog ground if LSRP_MODE = 00.

© 2008-2009 SiTel Semiconductor

8

Version: January 21, 2009 v1.0

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