AT45DB041E データシートの表示（PDF） - Unspecified

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AT45DB041E

4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory

Unspecified 

3. Memory Array

To provide optimal flexibility, the AT45DB041E memory array is divided into three levels of granularity comprising of

sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details

the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at

the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page

level.

Figure 3-1. Memory Architecture Diagram

Sector Architecture

Sector 0a = 8 pages

2,048/2,112 bytes

Sector 0a

Sector 0b = 248 pages

63,488/65,472 bytes

Sector 1 = 256 pages

65,536/67,584 bytes

Sector 2 = 256 pages

65,536/67,584 bytes

Sector 6 = 256 pages

65,536/67,584 bytes

Block Architecture

Block 0

Block 1

Block 2

Block 30

Block 31

Block 32

Block 33

Block 62

Block 63

Block 64

Block 65

8 Pages

Page Architecture

Page 0

Page 1

Page 6

Page 7

Page 8

Page 9

Page 14

Page 15

Page 16

Page 17

Page 18

Sector 7 = 256 pages

65,536/67,584 bytes

Block 254

Block 255

Block = 2,048/2,112 bytes

Page 2,046

Page 2,047

Page = 256/264 bytes

AT45DB041E

5

8783L–DFLASH–7/2017

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