202AI データシートの表示（PDF） - Integrated Device Technology

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202AI

Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

Integrated Device Technology 

IDT8SLVP2102I Data Sheet

LOW PHASE NOISE, DUAL 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

The IDT8SLVP2102I inputs can be interfaced to LVPECL, LVDS,

CML or LVCMOS drivers. Figure 1A illustrates how to DC couple a

single LVCMOS input to the IDT8SLVP2102I. The value of the series

resistance RS is calculated as the difference between the

transmission line impedance and the driver output impedance. This

resistor should be placed close to the LVCMOS driver. To avoid

cross-coupling of single-ended LVCMOS signals, apply the LVCMOS

signals to no more than one PCLK input.

A practical method to implement Vth is shown in Figure 1B below.

The reference voltage Vth = V1 = VCC/2, is generated by the bias

resistors R1 and R2. The bypass capacitor (C1) is used to help filter

noise on the DC bias. This bias circuit should be located as close to

the input pin as possible.

The ratio of R1 and R2 might need to be adjusted to position the V1

in the center of the input voltage swing. For example, if the input clock

swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted

to set V1 at 1.25V. The values below apply when both the

single-ended swing and VCC are at the same voltage.

Figure 1A. DC-Coupling a Single LVCMOS Input to the

IDT8SLVP2102I

When using single-ended signaling, the noise rejection benefits of

differential signaling are reduced. Even though the differential input

can handle full rail LVCMOS signaling, it is recommended that the

amplitude be reduced, particularly if both input references are

LVCMOS to minimize cross talk. The datasheet specifies a lower

differential amplitude, however this only applies to differential signals.

For single-ended applications, the swing can be larger, however VIL

cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.

Figure 1B shows a way to attenuate the PCLK input level by a factor

of two as well as matching the transmission line between the

LVCMOS driver and the IDT8SLVP2102I at both the source and the

load. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. R3 and R4 in parallel should equal

the transmission line impedance; for most 50 applications, R3 and

R4 will be 100. The values of the resistors can be increased to

reduce the loading for slower and weaker LVCMOS driver.

Though some of the recommended components of Figure 1B might

not be used, the pads should be placed in the layout so that they can

be utilized for debugging purposes. The datasheet specifications are

characterized and guaranteed by using a differential signal.

Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the IDT8SLVP2102I

IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014

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©2014 Integrated Device Technology, Inc.

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