24AA01-/SM データシートの表示（PDF） - Microchip Technology

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24AA01-/SM

1K I2C™ Serial EEPROM

Microchip Technology 

24AA01/24LC01B

1.2 AC Characteristics

AC CHARACTERISTICS

VCC = +1.8V to +5.5V

Industrial (I):

TAMB = -40°C to +85°C

Automotive (E): TAMB = -40°C to +125°C

Param.

No.

Sym

Characteristic

Min

Typ Max Units

Conditions

1

FCLK Clock frequency

—

—

—

—

2

THIGH Clock high time

600

—

4000

—

3

TLOW Clock low time

1300

—

4700

—

4

TR SDA and SCL rise time

—

—

(Note 1)

—

—

5

TF SDA and SCL fall time

—

—

—

6 THD:STA START condition hold

time

600

—

4000

—

7 TSU:STA START condition setup

600

—

time

4700

—

8 THD:DAT Data input hold time

0

—

—

9 TSU:DAT Data input setup time

100

—

250

—

10 TSU:STO STOP condition setup

600

—

time

4000

—

11

TAA Output valid from clock

—

—

(Note 2)

—

—

12

TBUF Bus free time: Time the

1300

—

bus must be free before 4700

—

a new transmission can

start

13

TOF Output fall time from VIH 20+0.1CB —

minimum to VIL maxi-

—

—

mum

14

TSP Input filter spike

suppression

(SDA and SCL pins)

—

—

400

100

—

—

—

—

300

1000

300

kHz 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC <2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns (Note 1)

—

ns 2.5V ≤ VCC ≤ 5.5V

—

1.8V ≤ VCC < 2.5V (24AA01)

—

ns 2.5V ≤ VCC ≤ 5.5V

—

1.8V ≤ VCC < 2.5V (24AA01)

—

ns (Note 2)

—

—

—

—

900

3500

—

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA01)

250

ns 2.5V ≤ VCC ≤ 5.5V

250

1.8V ≤ VCC < 2.5V (24AA01)

50

ns (Notes 1 and 3)

15

TWC Write cycle time (byte or

—

page)

—

5

ms —

16

— Endurance

1M

—

— cycles 25°C, VCC = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on Microchip’s website:

www.microchip.com.

 2002 Microchip Technology Inc.

DS21711A-page 3

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