MT28S2M32B1LC データシートの表示（PDF） - Micron Technology

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MT28S2M32B1LC

SYNCFLASH® MEMORY

Micron Technology 

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM INTERFACE

FUNCTIONAL DESCRIPTION

In general, the 64Mb SyncFlash memory devices

(1 Meg x 16 x 4 banks, 512K x 32 x 4 banks) are config-

ured as a quad-bank, nonvolatile SDRAM that operate

at 3.0V–3.6V and include a synchronous interface (all

signals are registered on the positive edge of the clock

signal, CLK). Each of the x16’s 16,777,216-bit banks is

organized as 4,096 rows by 256 columns by 16 bits.

Each of the x32’s 16,777,216-bit banks is organized as

2,048 rows by 256 columns by 32 bits.

Read accesses to the SyncFlash memory are identi-

cal to SDR SDRAM operation. Burst accesses start at a

selected location and continue for a programmed num-

ber of locations in a programmed sequence. Accesses

begin with the registration of an ACTIVE command,

followed by a READ command. The address bits regis-

tered coincident with the ACTIVE command are used

to select the bank and row to be accessed (BA0 and BA1

select the bank; x32: A0–A10, x16: A0–A11 select the

row). The address bits (A0–A7) registered coincident

with the READ command are used to select the starting

column location for the burst access.

All non-READ operations are controlled with either

an HCS or an SCS. Both the HCS and an SCS interface

can be used to initiate any of the internal program,

erase, initialization, or status operations. The term Flash

command sequence (FCS) refers to either HCS or SCS

operation.

Prior to normal operation, the SyncFlash memory

must be initialized. The following sections provide

detailed information covering device initialization, reg-

ister definition, command descriptions, and device op-

eration.

Initialization

The device power-up procedure can be defined two

ways. The first is a hardware initiated power-up, where

power is applied to VCC, VCCQ, and VCCP (simulta-

neously). Then, with the clock stable, RP# must be

brought from LOW to HIGH. After RP# transitions HIGH,

the power-up initialization process will complete within

100µs. The second procedure is defined as a software

initiated power-up. In this case the initialization is

performed using the INITIALIZE DEVICE FCS opera-

tion. When the INITIALIZE DEVICE command is used,

the RP# pin does not require the LOW-to-HIGH transi-

tion typically required for initialization. After the INI-

TIALIZE DEVICE command has been issued, the

power-up initialization process will complete within

100µs.

Early completion of either initialization procedure

can be detected by polling SR7 in the status register.

After initialization, the SyncFlash device is in standby

mode and ready for mode register programming or an

executable command. After initial programming of the

nvmode register, the contents are automatically loaded

into the mode register during initialization and the

device will power-up in the programmed state.

Note that when VCC is greater than 2.7V, either of the

initialization procedures can be issued.

Register Definition

MODE REGISTER

The mode register is used to define the specific mode

of operation of the SyncFlash memory. This definition

includes the selection of a burst length, a burst type, a

CAS latency, and an operating mode, as shown in Fig-

ure 1. The mode register is programmed via the LOAD

MODE REGISTER command and will retain the stored

information until it is reprogrammed. The nvmode reg-

ister settings are transferred into the mode register

during initialization. The contents of the mode register

may be copied into the nvmode register with a PRO-

GRAM NVMODE REGISTER command. Details on erase

nvmode register and program nvmode register

command sequences are found in the Command Ex-

ecution section of the Flash Memory Functional

Description.

Mode register bits M0–M2 specify the burst length,

M3 specifies the burst type (sequential or interleaved),

M4–M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9 specifies the WRITE burst mode,

and M10 and M11 are reserved for future use.

The mode register must be loaded when all banks

are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating

either of these requirements will result in unspecified

operation.

BURST LENGTH

Read and write accesses to the SyncFlash memory

are burst oriented, with the burst length being pro-

grammable, as shown in Figure 1. The burst length

determines the maximum number of column locations

that can be accessed for a given READ or WRITE com-

mand. Burst lengths of 1, 2, 4, or 8 locations are avail-

able for both the sequential and the interleaved burst

types (read or write), and a full-page burst is available

for the sequential type (read only). The full-page burst

can be used in conjunction with the BURST TERMI-

NATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

64Mb: x16, x32 SyncFlash

MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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