MT28S2M32B1LC データシートの表示（PDF） - Micron Technology
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MT28S2M32B1LC Datasheet PDF : 60 Pages
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READs
Read bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command.
During read bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each sub-
sequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
one, two and three CAS latency settings.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any read burst may be truncated with a
subsequent READ command, and data from a fixed-
length read burst may be immediately followed by data
from a subsequent READ command. In either case, a
continuous flow of data can be maintained. The first
data element from the new burst follows either the last
element of a completed burst, or the last desired data
element of a longer burst that is being truncated.
Figure 5
READ Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A7
BA0, BA1
COLUMN
ADDRESS
BANK
ADDRESS
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
The new READ command should be issued x cycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of one,
two and three; data element n + 3 is either the last of a
burst of four, or the last desired of a longer burst. The
SyncFlash memory uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initi-
ated on any clock cycle following a previous READ com-
mand. Full-speed, random read accesses within a page
can be performed as shown in Figure 8, or each subse-
quent READ may be performed to a different bank.
CLK
COMMAND
DQ
Figure 6
CAS Latency
T0
T1
T2
READ
tLZ
tAC
NOP
tOH
DOUT
CAS Latency = 1
T0
T1
T2
T3
CLK
COMMAND
DQ
READ
NOP
tLZ
tAC
CAS Latency = 2
NOP
tOH
DOUT
CLK
COMMAND
T0
READ
DQ
T1
T2
NOP
NOP
tLZ
tAC
CAS Latency = 3
T3
T4
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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