MT48LC4M32LFFC-10 データシートの表示（PDF） - Micron Technology

部品番号

コンポーネント説明

メーカー

MT48LC4M32LFFC-10

SYNCHRONOUS DRAM

Micron Technology 

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

BALL DESCRIPTIONS

54-BALL VFBGA

F2

F3

G9

F7, F8, F9

E8, F1

G7, G8

H7, H8, J8, J7, J3, J2,

H3, H2, H1, G3, H9, G2,

A8, B9, B8, C9, C8, D9,

D8, E9, E1, D2, D1, C2,

C1, B2, B1, A2

E2, G1

A7, B3, C7, D3

A3, B7, C3, D7,

A9, E7, J9

A1, E3, J1

SYMBOL

CLK

CKE

CS#

CAS#, RAS#,

WE#

LDQM,

UDQM

BA0, BA1

A0–A11

DQ0–DQ15

TYPE

Input

Input

Input

Input

Input

Input

Input

I/O

DESCRIPTION

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where

CKE becomes asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down and self refresh

modes, providing low standby power. CKE may be tied HIGH.

Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS# provides for external bank selection on systems with multiple banks. CS#

is considered part of the command code.

Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the

command being entered.

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for

write accesses and an output enable signal for read accesses. Input data is

masked during a WRITE cycle. The output buffers are placed in a High-Z state

(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–

DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered

same state when referenced as DQM.

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command

Address Inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A8; with

A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

Data Input/Output: Data bus

NC

VDDQ

VSSQ

VDD

VSS

– No Connect: These pins should be left unconnected.

G1 is a no connect for this part but may be used as A12 in future designs.

Supply DQ Power: Isolated power on the die to improve noise immunity.

Supply DQ Ground: Isolated power on the die to improve noise immunity.

Supply Power Supply: Voltage dependant on option.

Supply Ground.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

Share Link: