PDM41024SA10SO データシートの表示（PDF） - Paradigm Technology
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PDM41024SA10SO Datasheet PDF : 8 Pages
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PDM41024
Read Cycle No. 1(4, 5)
ADDR
DOUT
Read Cycle No. 2(2, 4, 6)
ADDR
CE1
CE2
OE
DOUT
tRC
tAA
tOH
PREVIOUS DATA VALID
tRC
tAA
tACE
tLZCE
tLZOE
tAOE
DATA VALID
tHZCE
tHZOE
DATA VALID
AC Electrical Characteristics
Description
-10(7)
-12(7)
-15
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC
10
12
15
ns
Address access time
tAA
10
12
15 ns
Chip enable access time
tACE
10
12
15 ns
Output hold from address change
tOH
3
3
3
ns
Chip enable to output in low Z(1,3)
tLZCE
5
5
5
ns
Chip disable to output in high Z(1,2,3)
tHZCE
6
6
7 ns
Chip enable to power up time(3)
tPU
0
0
0
ns
Chip disable to power down time(3)
tPD
10
12
15 ns
Output enable access time
tAOE
6
6
6 ns
Output enable to output in low Z (1,3)
tLZOE
0
0
0
ns
Output disable to output in high Z(1,3) tHZOE
6
6
6 ns
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Rev. 3.3 - 4/09/98
1
2
3
4
5
6
7
8
9
10
11
12
5
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