M29W002BT データシートの表示（PDF） - STMicroelectronics

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M29W002BT

2 Mbit (256Kb x8, Boot Block) Low Voltage Single Supply Flash Memory

STMicroelectronics 

M29W002BT, M29W002BB

Figure 2. TSOP Connections

A16 1

40 A17

A15

VSS

A14

NC

A13

NC

A12

A10

A11

DQ7

A9

DQ6

A8

DQ5

W

DQ4

RP 10 M29W002BT 31 VCC

NC 11 M29W002BB 30 VCC

RB

NC

NC

DQ3

A7

DQ2

A6

DQ1

A5

DQ0

A4

G

A3

VSS

A2

E

A1 20

21 A0

AI02956

SUMMARY DESCRIPTION

The M29W002B is a 2 Mbit (256Kb x8) non-vola-

tile memory that can be read, erased and repro-

grammed. These operations can be performed

using a single low voltage (2.7 to 3.6V) supply. On

power-up the memory defaults to its Read mode

where it can be read in the same way as a ROM or

EPROM. The M29W002B is fully backward com-

patible with the M29W002.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ7 Data Inputs/Outputs

E

Chip Enable

G

Output Enable

W

Write Enable

RP

Reset/Block Temporary Unprotect

RB

Ready/Busy Output

VCC

Supply Voltage

VSS

Ground

NC

Not Connected Internally

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3A and 3B, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32 Kbyte is a small Main Block where

the application may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in a TSOP40 (10 x 20mm)

package and it is supplied with all the bits erased

(set to ’1’).

2/20

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