SST31LF021-300-4E-WH(2001) データシートの表示（PDF） - Silicon Storage Technology
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SST31LF021-300-4E-WH Datasheet PDF : 24 Pages
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
SST31LF021E-300
Symbol Parameter
Min
Max
Min
Max
TRCS
TAAS
TBES
TOES
TBLZS1
TOLZS1
TBHZS1
TOHZS1
TOHS
Read Cycle Time
Address Access Time
Bank Enable Access Time
Output Enable Access Time
BES# to Active Output
Output Enable to Active Output
BES# to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
70
300
70
300
70
300
35
150
0
15
0
15
25
30
25
30
0
10
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
T9.4 392
TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
SST31LF021E-300
Symbol Parameter
Min
Max
Min
Max
TWCS
Write Cycle Time
70
300
TBWS
Bank Enable to End-of-Write
60
230
TAWS
Address Valid to End-of-Write
60
230
TASTS
Address Set-up Time
0
0
TWPS
Write Pulse Width
60
200
TWRS
Write recovery Time
0
0
TDSS
Data Set-up Time
30
150
TDHS
Data Hold from Write Time
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
T10.4 392
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
SST31LF021E-300
Symbol Parameter
Min
Max
Min
Max
Units
TRC
TBE
TAA
TOE
TBLZ1
TOLZ1
TBHZ1
TOHZ1
TOH1
Read Cycle Time
Bank Enable Access Time
Address Access Time
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
70
300
70
300
70
300
40
150
0
0
0
0
15
60
15
60
0
0
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
ns
ns
ns
ns
ns
ns
ns
ns
ns
T11.3 392
©2001 Silicon Storage Technology, Inc.
9
S71137-03-000 10/01 392
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