MT46V16M8 データシートの表示（PDF） - Micron Technology
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MT46V16M8 Datasheet PDF : 68 Pages
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PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. The 128Mb DDR SDRAM is internally
configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The ad-
dress bits registered coincident with the READ or WRITE
command are used to select the starting column loca-
tion for the burst access.
Prior to normal operation, the DDR SDRAM must
be initialized. The following sections provide detailed
information covering device initialization, register defi-
nition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Power must first be applied to VDD and VDDQ
simultaneously, and then to VREF (and to the system
VTT). VTT must be applied after VDDQ to avoid device
latch-up, which may cause permanent damage to the
device. VREF can be applied any time after VDDQ but is
expected to be nominally coincident with VTT. Except
for CKE, inputs are not recognized as valid until after
VREF is applied. CKE is an SSTL_2 input but will detect
an LVCMOS LOW level after VDD is applied. Maintain-
ing an LVCMOS LOW level on CKE during power-up
is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until
driven in normal operation (by a read access). After all
power supply and reference voltages are stable, and the
clock is stable, the DDR SDRAM requires a 200µs delay
prior to applying an executable command.
Once the 200µs delay has been satisfied, a DESE-
LECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP com-
mand, a PRECHARGE ALL command should be ap-
plied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by
another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL
and to program the operating parameters. Two-hun-
dred clock cycles are required between the DLL reset
and any READ command. A PRECHARGE ALL com-
mand should then be applied, placing the device in the
all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed (tRFC must be satisfied.) Addition-
ally, a LOAD MODE REGISTER command for the
mode register with the reset DLL bit deactivated (i.e., to
program operating parameters without resetting the
DLL) is required. Following these requirements, the
DDR SDRAM is ready for normal operation.
REGISTER DEFINITION
MODE REGISTER
The mode register is used to define the specific mode
of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 1. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed
correctly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A11 specify the
operating mode.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 1. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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