MC100E183FN データシートの表示（PDF） - Motorola => Freescale
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MC100E183FN Datasheet PDF : 8 Pages
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MC44824/25
Bits T10, T11: Control the Reference Ratio
T10
T11
Division Ratio
0
0
512
0
1
1024
1
0
1024
1
1
512
Bit T13: Switches the Internal Signals Fref and FBY2 to
Bit T13: the Band Buffer Outputs (Test)
T13 = 0
T13 = 1
Normal Operation
Test Mode
Fref Output at B7
FBY2 Output at B2
Bits B2 and B7 have to be “Off”, B2 = B7 = 0 in the test mode.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider, divided by two.
Bit T14: Controls the Charge Pump Current of the
Bit T14: Phase Comparator
T14 = 0
T13 = 1
Pump Current 40 µA Typical
Pump Current 125 µA Typical
The Band Buffers
BA_Band Information
MC44824 14 Pin version
B7 X X X X B2 B1 X ACK
MC44825 16 Pin version
B7 X X B4 X B2 B1 B0 ACK
The band buffers are open collector buffers and are active
“low” at Bn = 1. They are designed for 10 mA with a typical
“On” resistance of 160 Ω. These buffers are designed to
withstand relative high output voltage in the “Off” state.
B2 and B7 buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit B2 and/or B7 have to be zero if the buffers are used
for these additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division
ratio out of the latches B. Latches B are loaded from latches
A by means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
Minimum Ratio 17
Where N0 … N14 are the different bits for frequency
information.
The counter may be used for any ratio between 17 and
32767 and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the I2C bus.
At power–on, the whole bus receiver is reset and the
programmable divider is set to a counting ration of N = 256 or
higher.
The first I2C message must be sent only when the
POWER ON RESET is completed.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Tuning Voltage Amplifier
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external NPN with a pull–up resistor to generate the tuning
voltage.
The amplifier can be switched “Off” through bit T8. When
bit T8 is “One”, the amplifier is “Off”. The tuning voltage is
then pulled high by the external pull–up resistor.
Figure 5 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 5 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground “or
between Pins 2 and 3” through a series capacitor. The crystal
oscillates in its series resonance mode.
The voltage at Pin 13 XTAL1, has low amplitude and low
harmonic distortion.
Pin XTAL2 is the internal ground of the oscillator; it is
connected internally to ground Pin 13 (15).
6
MOTOROLA ANALOG IC DEVICE DATA
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