28F002BL-T150 データシートの表示（PDF） - Intel

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28F002BL-T150

2-MBIT (128K x 16, 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F200BL-T B 28F002BL-T B

3 1 2 2 28F002BL-T Memory Map

The 28F002BL-T device has the 16-Kbyte boot

block located trom 3C000H to 3FFFFH to accom-

modate those microprocessors that boot from the

top of the address map In the 28F002BL-T the first

8-Kbyte parameter block resides in memory space

from 3A000H to 3BFFFH The second 8-Kbyte pa-

rameter block resides in memory space from

38000H to 39FFFH The 96-Kbyte main block re-

sides in memory space from 20000H to 37FFFH

The 128-Kbyte main block resides in memory space

from 00000H to 1FFFFH

3FFFFH

3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

20000H

1FFFFH

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

00000H

Figure 11 28F002BL-T Memory Map

4 0 PRODUCT FAMILY PRINCIPLES

OF OPERATION

Flash memory augments EPROM functionality with

in-circuit electrical write and erase The 2-Mbit flash

family utilizes a Command User Interface (CUI) and

internally generated and timed algorithms to simplify

write and erase operations

The CUI allows for fixed power supplies during era-

sure and programming and maximum EPROM com-

patibility

In the absence of high voltage on the VPP pin the

2-Mbit flash family will only successfully execute the

following commands Read Array Read Status Reg-

ister Clear Status Register and Intelligent ldentifier

mode The device provides standard EPROM read

standby and output disable operations Manufactur-

er Identification and Device Identification data can

be accessed through the CUI or through the stan-

dard EPROM A9 high voltage access (VID) (for

PROM programmer equipment)

The same EPROM read standby and output disable

functions are available when high voltage is applied

to the VPP pin In addition high voltage on VPP al-

lows write and erase of the device All functions as-

sociated with altering memory contents write and

erase Intelligent Identifier read and Read Status are

accessed via the CUI

The purpose of the Write State Machine (WSM) is to

completely automate the write and erasure of the

device The WSM will begin operation upon receipt

of a signal from the CUI and will report status back

through a Status Register The CUI will handle the

WE interface to the data and address latches as

well as system software requests for status while the

WSM is in operation

4 1 28F200BL Bus Operations

Flash memory reads erases and writes in-system

via the local CPU All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles

16

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