28F002BL-T150 データシートの表示（PDF） - Intel

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28F002BL-T150

2-MBIT (128K x 16, 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F200BL-T B 28F002BL-T B

28F002BL Products

The manufacturer and device codes are also read

via the CUI or by taking the A9 pin to 12V Writing

90H to the CUI places the device into Intelligent

Identifier read mode A read of location 00000H

outputs the manufacturer’s identification code 89H

and location 00001H outputs the device code 7CH

for 28F002BL-T 7DH for 28F002BL-B

4 4 Write Operations

Commands are written to the CUI using standard mi-

croprocessor write timings The CUI serves as the

interface between the microprocessor and the inter-

nal chip operation The CUI can decipher Read Ar-

ray Read Intelligent Identifier Read Status Register

Clear Status Register Erase and Program com-

mands In the event of a read command the CUI

simply points the read path at either the array the

Intelligent Identifier or the status register depending

on the specific read command given For a program

or erase cycle the CUI informs the write state ma-

chine that a write or erase has been requested Dur-

ing a program cycle the Write State Machine will

control the program sequences and the CUI will only

respond to status reads During an erase cycle the

CUI will respond to status reads and erase suspend

After the Write State Machine has completed its

task it will allow the CUI to respond to its full com-

mand set The CUI will stay in the current command

state until the microprocessor issues another com-

mand

The CUI will successfully initiate an erase or write

operation only when VPP is within its voltage range

Depending upon the application the system design-

er may choose to make the VPP power supply

switchable available only when memory updates

are desired The system designer can also choose

to ‘‘hard-wire’’ VPP to 12V The 2-Mbit flash family is

designed to accommodate either design practice It

is recommended that RP be tied to logical Reset

for data protection during unstable CPU reset func-

tion as described in the ‘‘Product Family Overview’’

section

4 4 1 BOOT BLOCK WRITE OPERATIONS

In the case of Boot Block modifications (write and

erase) RP is set to VHH e 12V typically in addi-

tion to VPP at high voltage However if RP is not at

VHH when a program or erase operation of the boot

block is attempted the corresponding status register

bit (Bit 4 for Program and Bit 5 for Erase refer to

Table 5 for Status Register Definitions) is set to indi-

cate the failure to complete the operation

4 4 2 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) serves as the

interface to the microprocessor The CUI points the

read write path to the appropriate circuit block as

described in the previous section After the WSM

has completed its task it will set the WSM Status bit

to a ‘‘1’’ which will also allow the CUI to respond to

its full command set Note that after the WSM has

returned control to the CUI the CUI will remain in its

current state

4 4 2 1 Command Set

Command

Codes

Device Mode

00

Invalid Reserved

10

Alternate Program Setup

20

Erase Setup

40

Program Setup

50

Clear Status Register

70

Read Status Register

90

Intelligent Identifier

B0

Erase Suspend

D0

Erase Resume Erase Confirm

FF

Read Array

4 4 2 2 Command Function Descriptions

Device operations are selected by writing specific

commands into the CUI Table 4 defines the 2-Mbit

flash family commands

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