AT24C64-10TC データシートの表示（PDF） - Atmel Corporation
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AT24C64-10TC Datasheet PDF : 15 Pages
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AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
1.8-volt
2.7-, 2.5-volt
5.0-volt
Symbol
Parameter
Min Max Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
100
100
400
kHz
Clock Pulse Width Low
4.7
4.7
1.2
µs
Clock Pulse Width High
Noise Suppression Time(1)
4.0
4.0
0.6
µs
100
100
50
ns
Clock Low to Data Out Valid
0.1 4.5 0.1
4.5
0.1 0.9
µs
Time the bus must be free
before a new transmission can start(1)
4.7
4.7
1.2
µs
tHD.STA
Start Hold Time
4.0
4.0
tSU.STA
Start Set-up Time
4.7
4.7
tHD.DAT
Data In Hold Time
0
0
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
200
200
1.0
300
tSU.STO
Stop Set-up Time
4.7
4.7
tDH
Data Out Hold Time
100
100
tWR
Endurance(1)
Write Cycle Time
5.0V, 25°C, Page Mode
20
1M
1M
Note: 1. This parameter is characterized and is not 100% tested.
0.6
µs
0.6
µs
0
µs
100
ns
1.0
0.3
µs
300
300
ns
0.6
µs
50
ns
10
10
ms
1M
Write Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
4
AT24C32/64
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