24AA164 データシートの表示（PDF） - Microchip Technology
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24AA164 Datasheet PDF : 12 Pages
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24AA164
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
STANDARD
MODE
VCC = 4.5-5.5V
FAST MODE
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
THIGH
4000
—
600
—
ns
Clock low time
TLOW
4700
—
1300
—
ns
SDA and SCL rise time
TR
—
1000
—
300 ns (Note 1)
SDA and SCL fall time
TF
—
300
—
300 ns (Note 1)
START condition hold
THD:STA 4000
—
600
—
ns After this period the first
time
clock pulse is generated
START condition setup TSU:STA 4700
—
600
—
ns Only relevant for repeated
time
START condition
Data input hold time
THD:DAT
0
—
0
—
ns
Data input setup time
TSU:DAT
250
—
100
—
ns
STOP condition setup
TSU:STO 4000
—
600
—
ns
time
Output valid from clock
TAA
—
3500
—
900 ns (Note 2)
Bus free time
TBUF
4700
—
1300
—
ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
TOF
min to VIL max
—
250 20 + 0.1 250
ns (Note 1), CB ≤ 100 pF
CB
Input filter spike suppres- TSP
—
50
—
50
ns (Note 3)
sion (SDA and SCL pins)
Write cycle time
TWR
—
10
—
10
ms Byte or Page mode
Endurance
—
1M
—
1M
— cycles 25°C, Vcc = 5.0V, Block
Mode ((Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS =specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:STA
THD:DAT
TSU:DAT TSU:STO
SDA
IN
TSP
TAA
TAA
TBUF
SDA
OUT
© 1999 Microchip Technology Inc.
DS21100F-page 3
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