24AA65 データシートの表示（PDF） - Microchip Technology
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24AA65 Datasheet PDF : 24 Pages
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24AA65/24LC65/24C65
TABLE 1-2: AC CHARACTERISTICS
Parameter
VCC = 1.8V-6.0V VCC = 4.5-6.0V
Symbol STD. Mode
FAST Mode
Units
Remarks
Min Max
Min Max
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
FCLK
—
100
—
400 kHz
THIGH
4000
—
600
—
ns
TLOW
4700
—
1300
—
ns
TR
— 1000
—
300
ns (Note 1)
TF
—
300
—
300
ns (Note 1)
THD:STA 4000
—
600
—
ns After this period the first
clock pulse is generated
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
TSU:STA 4700
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
0
250
4000
—
4700
Output fall time from VIH min to TOF
VIL max
Input filter spike suppression TSP
(SDA and SCL pins)
Write cycle time
TWR
Endurance
High Endurance Block
Rest of Array
—
50
—
10M
1M
—
—
—
—
3500
—
250
—
5
—
—
600
0
100
600
—
1300
20 + 0.1
CB
50
—
10M
1M
—
ns Only relevant for
repeated Start condition
—
ns
—
ns
—
ns
900
ns (Note 2)
—
ns Time the bus must be
free before a new
transmission can start
250
ns (Note 1), CB ≤ 100 pF
—
ns (Note 3)
5 ms/page (Note 4)
— cycles 25°C, (Note 5)
—
Note 1:
2:
3:
4:
5:
Not 100 percent tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.
FIGURE 1-2:
BUS TIMING DATA
TF
SCL
TSU:STA
SDA
IN
SDA
OUT
TSP
TAA
TLOW
THD:STA
THIGH
THD:DAT
TAA
TR
TSU:DAT TSU:STO
TBUF
DS21073J-page 4
2003 Microchip Technology Inc.
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