24C32ASM データシートの表示（PDF） - Microchip Technology
部品番号
コンポーネント説明
メーカー
24C32ASM Datasheet PDF : 12 Pages
| |||
24C32A
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
Vcc = 4.5-5.5
Min
Max
Units
Remarks
Clock frequency
FCLK
—
100
kHz
Clock high time
THIGH
4000
—
ns
Clock low time
TLOW
4700
—
ns
SDA and SCL rise time
TR
—
1000
ns (Note 1)
SDA and SCL fall time
TF
—
300
ns (Note 1)
START condition hold time
THD:STA
4000
—
ns After this period the first clock
pulse is generated
START condition setup time
TSU:STA
4700
—
ns Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
ns
Data input setup time
TSU:DAT
250
—
ns
STOP condition setup time
TSU:STO
4000
—
ns
Output valid from clock
TAA
—
3500
ns (Note 2)
Bus free time
TBUF
4700
—
ns Time the bus must be free before
a new transmission can start
Output fall time from VIH min to
TOF
VIL max
—
250
ns (Note 1), CB ≤ 100 pF
Input filter spike suppression
TSP
—
50
ns (Note 3)
(SDA and SCL pins)
Write cycle time
TWR
—
5
ms
Endurance
—
1M
—
cycles 25°C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF
TLOW
THIGH
SCL
TSU:STA
SDA
IN
TSP
THD:STA
THD:DAT
SDA
OUT
TAA
THD:STA
TAA
TR
TSU:DAT
TSU:STO
TBUF
2004 Microchip Technology Inc.
DS21163E-page 3
Share Link: 