24C32AT データシートの表示（PDF） - Microchip Technology

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24C32AT

32K 5.0V I2C™ Serial EEPROM

Microchip Technology 

7.0 PIN DESCRIPTIONS

7.1 A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24C32A for multiple

device operation and conform to the 2-wire bus stan-

dard. The levels applied to these pins define the

address block occupied by the device in the address

map. A particular device is selected by transmitting the

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-3).

7.2 SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for

400 kHz)

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL HIGH are

reserved for indicating the START and STOP condi-

tions.

7.3 SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

7.4 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations

are not affected.

24C32A

8.0 NOISE PROTECTION

The SCL and SDA inputs have filter circuits which sup-

press noise spikes to ensure proper device operation

even on a noisy bus. All I/O lines incorporate Schmitt

triggers for 400 kHz (Fast Mode) compatibility.

9.0 POWER MANAGEMENT

This design incorporates a power standby mode when

the device is not in use and automatically powers off

after the normal termination of any operation when a

stop bit is received and all internal functions are com-

plete. This includes any error conditions, i.e., not

receiving an acknowledge or stop condition per the

two-wire bus specification. The device also incorpo-

rates VDD monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The

VDD monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-

sumption.

 2004 Microchip Technology Inc.

DS21163E-page 9

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