24C04A データシートの表示（PDF） - Unspecified

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24C04A

Two-Wire Serial EEPROM 4K, 8K and 16K (8-bit wide)

Unspecified 

24C04A, 24C08A, 24C16A

DEVICE ADDRESSING

The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read

or write command. The first four most significant bits of the device address must be 1010, which is common to all

serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are

to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an

ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However,

matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a

read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters

programming mode.

FT24C04A uses A2 (5th) and A1 (6th) device address bits. Only four FT24C04A devices can be wired-OR on the same

2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11

(b). Chip select address pin A0 is not used.

FT24C08A uses only A2 (5th) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire

bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select

address pins A1 and A0 are not used.

FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip

Select address pins A2, A1, and A0 are not used.

WRITE OPERATIONS

(A) BYTE WRITE

A byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM

device address and then a write command. If the device address bits match the chip select address, the EEPROM

device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word

address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then

transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the

micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed

programming mode during which all external inputs will be disabled. After a programming time of TWC, the byte

programming will finish and the EEPROM device will return to the STANDBY mode.

(B) PAGE WRITE

A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the

same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.

With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the

1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it

sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and

EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n  9th clock cycle.

After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page

programming completes after a time of TWC, the devices will return to the STANDBY mode.

© 2009 Fremont Micro Devices Inc.

DS3001M-page5

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