24C64 データシートの表示（PDF） - Microchip Technology

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24C64

64K SPI™ Bus Serial EEPROM

Microchip Technology 

25AA640/25LC640/25C640

3.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25xx640 contains a write enable latch. See

Table 3-3 for the Write Protect Functionality Matrix.

This latch must be set before any write operation will

be completed internally. The WREN instruction will set

the latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 3-4: WRITE ENABLE SEQUENCE

CS

SCK

01234567

SI

00000110

high impedance

SO

FIGURE 3-5: WRITE DISABLE SEQUENCE

CS

SCK

01234567

SI

0 0 0 0 0 1 10 0

high impedance

SO

DS21223A-page 8

Preliminary

© 1997 Microchip Technology Inc.

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