24LC21A データシートの表示（PDF） - Microchip Technology

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24LC21A

1K 2.5V Dual Mode I2C™ Serial EEPROM

Microchip Technology 

24LC21A

TABLE 1-2: AC CHARACTERISTICS

Parameter

Vcc= 2.5-5.5V Vcc= 4.5 - 5.5V

Symbol Standard Mode Fast Mode

Units

Remarks

Min Max Min Max

Clock frequency

FCLK

—

100

—

400 kHz

Clock high time

THIGH

4000

—

600

—

ns

Clock low time

TLOW

4700

—

1300

—

ns

SDA and SCL rise time TR

—

1000

—

300

ns (Note 1)

SDA and SCL fall time

TF

—

300

—

300

ns (Note 1)

Start condition hold time THD:STA 4000

—

600

—

ns After this period the first clock

pulse is generated

Start condition setup time TSU:STA 4700

—

600

—

ns Only relevant for repeated

Start condition

Data input hold time

THD:DAT

0

—

0

—

ns (Note 2)

Data input setup time

TSU:DAT 250

—

100

—

ns

Stop condition setup time TSU:STO 4000

—

600

—

ns

Output valid from clock TAA

—

3500

—

900

ns (Note 2)

Bus free time

TBUF

4700

—

1300

—

ns Time the bus must be free

before a new transmission

can start

Output fall time from VIH TOF

minimum to VIL maximum

—

250 20 + 0.1 250

ns (Note 1), CB ≤ 100 pF

CB

Input filter spike suppres- TSP

sion (SDA and SCL pins)

—

50

—

50

ns (Note 3)

Write cycle time

TWR

—

10

—

10

ms Byte or Page mode

Transmit-Only Mode Parameters

Output valid from VCLK TVAA

—

2000

—

1000

ns

VCLK high time

TVHIGH 4000

—

600

—

ns

VCLK low time

TVLOW

4700

—

1300

—

ns

VCLK setup time

TVHST

0

—

0

—

ns

VCLK hold time

TSPVL

4000

—

600

—

ns

Mode transition time

TVHZ

—

1000

—

500

ns

Transmit-only power-up

time

TVPU

0

—

0

—

ns

Input filter spike suppres- TSPV

sion (VCLK pin)

—

100

—

100

ns

Endurance

—

1M

—

1M

— cycles 25°C, Vcc = 5.0V, Block

mode (Note 4)

Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site.

 2003 Microchip Technology Inc.

DS21160F-page 3

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