25AA040A データシートの表示（PDF） - Microchip Technology

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25AA040A

4K SPI Bus Serial EEPROM

Microchip Technology 

BLOCK DIAGRAM

STATUS

Register

25AA040A/25LC040A

HV Generator

I/O Control

Logic

Memory X

Control

Logic Dec

EEPROM

Array

Page Latches

SI

SO

CS

SCK

HOLD

WP

VCC

VSS

Y Decoder

Sense Amp.

R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format

Description

READ

WRITE

WRDI

0000 A8011

0000 A8010

0000 x100

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Reset the write enable latch (disable write operations)

WREN

0000 x110

Set the write enable latch (enable write operations)

RDSR

0000 x101

Read STATUS register

WRSR

0000 x001

Write STATUS register

Note: A8 is the 9th address bit, which is used to address the entire 512 byte array.

x = don’t care.

FIGURE 2-1:

CS

READ SEQUENCE

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction+Address MSb

Lower Address Byte

0 0 0 0 A8 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0

High-Impedance

Data Out

76543210

 2003-2012 Microchip Technology Inc.

DS21827H-page 7

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