25LC128T(2007) データシートの表示（PDF） - Microchip Technology

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25LC128T
(Rev.:2007)

128K SPI Bus Serial EEPROM

Microchip Technology 

25AA128/25LC128

2.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25XX128 contains a write enable latch. See

Table 2-4 for the Write-Protect functionality matrix. This

latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

CS

SCK

01234567

SI

00000110

High-Impedance

SO

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

CS

SCK

01234567

SI

000001

00

High-Impedance

SO

© 2007 Microchip Technology Inc.

DS21831C-page 9

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