25AA640A(2008) データシートの表示（PDF） - Microchip Technology

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25AA640A
(Rev.:2008)

64K SPI Bus Serial EEPROM

Microchip Technology 

25AA640A/25LC640A

2.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS reg-

ister as shown in Table 2-2. The user is able to select

one of four levels of protection for the array by writing

to the appropriate bits in the STATUS register. The

array is divided up into four segments. The user has the

ability to write-protect none, one, two, or all four of the

segments of the array. The partitioning is controlled as

shown in Table 2-3.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the

programmable hardware write-protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pin is high or the WPEN

bit is low. When the chip is hardware write-protected,

only writes to nonvolatile bits in the STATUS register

are disabled. See Table 2-4 for a matrix of functionality

on the WPEN bit.

See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3: ARRAY PROTECTION

BP1

BP0

Array Addresses

Write-Protected

0

0

none

0

1

upper 1/4

(1800h-1FFFh)

1

0

upper 1/2

(1000h-1FFFh)

1

1

all

(0000h-1FFFh)

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

SCK

SI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Data to STATUS Register

0 00 00 0 01 7 6 54 3 2 10

High-Impedance

SO

Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register

sequence.

© 2008 Microchip Technology Inc.

DS21830D-page 11

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